CSS past paper

CSS Computer Science Paper II Past Paper 2025

CSS Computer Science Paper II 2025 carries 100 marks over 3 hours. It has 7 questions.

Marks: 100
Time: 3 hours
Questions: 7

Years

How to attempt: Attempt ONLY FOUR questions from PART-II by selecting TWO questions from EACH SECTION. ALL questions carry EQUAL marks.

Questions

Question 1 (Part I) is the paper's MCQs, which are not reproduced here.

SECTION – A

Q. 2
- (a)
  An instruction requires five stages to execute:
  (3)
  Stage-1 (instruction fetch) requires = 30 ns
  Stage-2 (instruction decode) = 9 ns
  Stage-3 (instruction execute) = 20 ns
  Stage-4 (Memory access) = 35 ns
  Stage-5 (Store results) = 10 ns
  An instruction must proceed through the stages in sequence. What is the minimum asynchronous time for any single instruction to complete?
- (b)
  Consider a single-level cache with an access time of 2.5 ns, a line size of 64 bytes, and a hit ratio of $H = 0.95$ . Main memory uses a block transfer capability that has a firstword (4 bytes) access time of 50 ns and an access time of 5 ns for each word thereafter.
  - (i)
    What is the access time when there is a cache miss? Assume that the cache waits until the line has been fetched from main memory and then re-executes for a hit.
    (3)
  - (ii)
    Suppose that increasing the line size to 128 bytes increases the $H$ to 0.97. Does this reduce the average memory access time?
    (4)
- (c)
  - (i)
    Compare the set of addressing modes of RISC and CISC machines. Give one example of addressing modes used in RISC and CISC respectively.
    (5)
  - (ii)
    Explain Parallel Processing, and also draw pipeline processing for instruction: Ai*Bi+Ci
    (5)
Q. 3
- (a)
  Answer the Following Questions:
  - (i)
    Is it possible for an organization’s Web server and mail server to have exactly the same alias for a hostname (for example, foo.com)? What would be the type for the RR that contains the hostname of the mail server?
    (2)
  - (ii)
    Draw the structure of Internet in terms of ISPs, also show the concept in terms of Edge and Core networks.
    (3)
  - (iii)
    A packet switch receives a packet to be forwarded. When the packet arrives, one other packet is halfway done being transmitted on this outbound link and four other packets are waiting to be transmitted in FIFO manner. Suppose all packets are 1,500 bytes and the link rate is 2 Mbps. What is the queuing delay for the packet?
    (3)
  - (iv)
    Why do HTTP, FTP, SMTP, and POP3 run on top of TCP rather than on UDP?
    (2)
- (b)
  - (i)
    Why do we need conditional GET when we have regular GET with respect to HTTP? What is its difference in comparison to GET?
    (4)
  - (ii)
    With respect to web caching, if an average object size is 100K bits and the average request rate from browsers to origin servers is 15/sec. Suppose RTT from an institutional router to any origin server is 2 sec. If LAN speed is 100Mbps and access link speed is 1.54 Mbps then with a cache hit of 50%, how much total delay will be there?
    (6)
Q. 4
- (a)
  A benchmark program is run on a 40 MHz processor. The executed program consists of 100,000 instruction executions, with the following instruction mix and clock cycle count:
  (10)
  Instruction Type Instruction Count Cycles per Instruction
  Integer arithmetic 45,000 1
  Data transfer 32,000 2
  Floating point 15,000 2
  Control transfer 8000 2
  Determine the effective CPI, MIPS rate, and execution time for this program.
- (b)
  What are the differences among sequential access, direct access, and random access? Also, write and explain the general relationship among access time, memory cost, and capacity.
  (10)
Q. 5
- (a)
  Consider the following pseudo code for producer and consumer:
  // producerdo{ // consumerdo{
  //produce an item // remove item from buffer
  //place in buffer // consumes item
  }while(true); }while(true);
  - (i)
    What is race condition?
    (2)
  - (ii)
    Is there any possibility of the race condition if two threads named producer and consumer simultaneously execute the above functions? Provide the reasoning in two-three sentences.
    (2)
  - (iii)
    Add the necessary synchronization in the above functions, you may use semaphores or mutex. You may provide just pseudo code or exact C/C++ code.
    (3)
  - (iv)
    Consider a process that uses a user level threading library to spawn 10 user level threads. The library maps these 10 threads on to 2 kernel threads. The process is executing on a 8-core system. What is the maximum number of threads of a process that can be executing in parallel?
    (3)
- (b)
  Consider a multi-level memory management scheme with the following format for virtual addresses:
  Virtual Page # Virtual Page # Offset
  (10 bits) (10 bits) (12 bits)
  Virtual addresses are translated into physical addresses of the following form:
  Physical Page # Offset
  (20 bits) (12 bits)
  Page table entries (PTE) are 32 bits and contain the 20-bit physical page number and OS bookkeeping bits (e.g., valid, dirty, used, etc.).
  - (i)
    How big is a page?
    (1)
  - (ii)
    What is the maximum amount of memory (in bytes) in a single virtual address space? Explain your answer.
    (3)
  - (iii)
    What is the maximum amount of physical memory (in bytes) that this memory management scheme supports? Explain your answer.
    (3)
  - (iv)
    Sketch the format of the page table for the multi-level virtual memory management scheme. Illustrate the process of resolving an address as well as possible. Assume there is no TLB or cache.
    (3)

Instruction Type	Instruction Count	Cycles per Instruction
Integer arithmetic	45,000	1
Data transfer	32,000	2
Floating point	15,000	2
Control transfer	8000	2

SECTION – B

Q. 6
- (a)
  Answer the questions i, ii, according to given schema.
  - (i)
    Display the length of first name and length of second name for employees where last name contains character ‘b’ after 3 $^{\text{rd}}$ position.
    (2)
  - (ii)
    Display job title, department name, employee last name, starting date for all jobs from 1992 to 1998.
    (3)
  - (iii)
    Differentiate between Left outer join, Right outer join and Full outer join. Explain your answer with the help of Venn Diagram.
    (5)
- (b)
  Provide brief answers to the following questions:
  - (i)
    Differentiate between Single row Sub-Query and Multi row Sub-Query and write a sample query too.
    (5)
  - (ii)
    Discuss the role of Primary Keys, foreign keys, and indexes in database schema. Also, explain their significance in ensuring data accuracy, enforcing referential integrity and improving query performance.
    (5)
Q. 7
- (a)
  In the context of compression, differentiate between coding, spatial and temporal redundancies.
  (6)
- (b)
  What is translation and scaling? Find the number of bits required to store a 256x256 image with 32 gray levels.
  (6)
- (c)
  What is Histogram equalization? Explain the process and discuss its uses.
  (8)
Q. 8
- (a)
  What is the role of requirement engineering in web engineering? List functional and non-functional requirements for a website.
  (6)
- (b)
  What are different security mechanisms used for encrypting the contents of a website? Explain any one in detail.
  (6)
- (c)
  Explain 3-tier web application architecture.
  (8)

Part-II is to be attempted on the separate Answer Book.
Attempt ONLY FOUR questions from PART-II by selecting TWO questions from EACH SECTION. ALL questions carry EQUAL marks.
All the parts (if any) of each Question must be attempted at one place instead of at different places.
Candidate must write Q. No. in the Answer Book in accordance with Q. No. in the Q.Paper.
No Page/Space be left blank between the answers. All the blank pages of Answer Book must be crossed.
Extra attempt of any question or any part of the attempted question will not be considered.

// producerdo{	// consumerdo{
//produce an item	// remove item from buffer
//place in buffer	// consumes item
}while(true);	}while(true);

Virtual Page #	Virtual Page #	Offset
(10 bits)	(10 bits)	(12 bits)